Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Intellectual property cores are often used in IC designs, including IC designs loaded into an FPGA or other PLD. An intellectual property core is a well-defined circuit or component provided by a vendor or third party that a user incorporates into the IC design. An IP core typically has several parameters that a user can specify, but the user does not typically change the IP core. IP cores can be considered building blocks to be used in the IC design (circuit) that provide specific, and often complex, functionality. Examples of IP cores include finite impulse response (“FIR”) filters, fast Fourier transforms (“FFTs”), and memory generators that allocate memory requirements to different physical memory arrays.
Rather than deriving an FIR filter from scratch, a circuit designer can load an FIR filter IP core into his IC design and specify the desired parameters for the FIR filter IP core, such as data bit width, coefficient bit width, number of filter taps, filter architecture, and sampling rate according to the user's intended function of the FIR filter in the IC design. An IC designer might want to know how an IP core parameter, such as the number of taps on an FIR filter, affects system performance, such as chip resources, power consumption, delay, clock rate, and latency.
However, understanding how the user-selected parameters of the IP core affect overall IC system performance is difficult because of the limited information that is available in conventional design tools. This type of information is conventionally provided to a designer in tabular form in documentation provided by the chip manufacturer or IP core supplier. Tables can be difficult to use because, after finding the correct table, the designer must accurately read the value from the correct row and column. Many parameters may be involved for complex IP cores, and table-based techniques can be error prone. For complex designs with large numbers of parameters, the number of parameter combinations can be in the millions, making it impractical to list the resources for all combinations.
For some IP cores, the vendor supplies fairly simple plots to help visualize how certain parameters affect resources. For example, the CORE GENERATOR tool available from XILINX, INC., of San Jose, Calif., provides plots to help visualize effects of parameters, such as resources versus latency in the floating point core. However, only a few parameters for a few resources are generally provided in graphical form.
Another technique is to run a complete tool flow (IC design implementation) for each parameter change, evaluating various selected parameter values against each other. Unfortunately, this is time consuming and can be very tedious for the designer, especially when a user wants to compare different sets of parameters, or when one parameter affects another.
It is desirable to estimate IC design performance according to selected parameters of an IP core in a manner that avoids the problems of the prior art.